>_<.

module tb();

initial begin
	$hello;
	#10	$finish;
end

endmodule

#include "vpi_user.h"

PLI_INT32 hello( PLI_BYTE8 *user_data ) {
	vpi_printf("\nHello PLI\n");

	return 0;
}	

void vpit_register_hello(void) {
    s_vpi_systf_data systf_data;
#ifndef ICARUS_VPI
    vpiHandle        systf_handle;
#endif

    systf_data.type        = vpiSysTask;
    systf_data.sysfunctype = 0;
    systf_data.tfname      = "$hello";
    systf_data.calltf      = hello;
    systf_data.compiletf   = 0;
    systf_data.sizetf      = 0;
    systf_data.user_data   = 0;
#ifndef ICARUS_VPI
    systf_handle = vpi_register_systf( &systf_data );
    vpi_free_object( systf_handle );
#else
    vpi_register_systf( &systf_data );
#endif
}

void (*vlog_startup_routines[])() = {
    vpit_register_hello,
    0
};

    always @ (posedge clock)
        q <= d;

    always @ (a or b) // this event list is missing signal sl
        if (sl)
            d = a;
        else
            d = b;

    // example of bad comments
    // add a and b together
        always @ (a or b)
            c = a + b;

    // Good commenting
    // 8 bit unsigned adder for data signals ‘a’ and ‘b’
    // output is sent to UART2
        always @ (a or b)
            c = a + b;

    always @ (c)
        if (c == 4’b0101)
            a = 2’bxx;
        else
            a = 2’b10;

    state_machine u1 (
        .sm_in (in1),
        .sm_clock (clk),
        .reset (reset),
        .sm_out (data_mux)
    );

// async active low reset d_ff
module d_ff(
      input        wire     clock
    , input        wire     reset
    , input        wire     d
    , output       reg      q
);

    always @(posedge clock or negedge reset) begin
        if(~reset) 
            q <= 1'b0;
        else
            q <= d;
    end
endmodule

// sync active low reset d_ff
module d_ff(
      input        wire       clock
    , input        wire       reset
    , input        wire       d
    , output       reg        q
);

    always @(posedge clock) begin
        if(~reset) 
            q <= 1'b0;
        else
            q <= d;
    end
endmodule

`include "timescale.v"

module tb();
    reg clock;
    reg d;
    wire q;

    initial begin
    	clock = 0;
    	d = 0;
    end

    always begin
    	#5	clock = ~clock;
    end

    initial begin
    	$dumpfile("sim.vcd");
    	$dumpvars(0, tb);

    	$monitor("TIME=%d clock=%d d=%d q=%d", $time, clock, d, q);

    	#60		d = 1;			
    	#60		d = 0;
    	#60		$finish;
    end

    d_ff Ud_ff(
    	  .clock(clock)
    	, .d(d)
    	, .q(q)
    );

endmodule

module d_ff(
    	  input 	wire	clock
    	, input		wire	d
    	, output	reg	q
);
    always @(negedge clock)
    	q <= d;

endmodule