>_<.

`include "timescale.v"

module tb();
    reg clock;
    reg d;
    wire q;

    initial begin
    	clock = 0;
    	d = 0;
    end

    always begin
    	#5	clock = ~clock;
    end

    initial begin
    	$dumpfile("sim.vcd");
    	$dumpvars(0, tb);

    	$monitor("TIME=%d clock=%d d=%d q=%d", $time, clock, d, q);

    	#60		d = 1;			
    	#60		d = 0;
    	#60		$finish;
    end

    d_ff Ud_ff(
    	  .clock(clock)
    	, .d(d)
    	, .q(q)
    );

endmodule

module d_ff(
    	  input 	wire	clock
    	, input		wire	d
    	, output	reg	q
);
    always @(negedge clock)
    	q <= d;

endmodule