합성 가능한 코드를 짜기위한 가이드라인이라구 한다능. 나도 어디선거 주워왔는데 쉽게 찾아볼 수 있게 블로그에 백ㅋ업ㅋ
Coding Guidelines
These coding guidelines assume that you are able to write correct synthesizeable code. You can always check the synthesizeablilty of your code by parsing it using the synthesis tool.
1. Use non-blocking assignments (<=) in clocked procedures. Don’t use blocking assignments (=).
always @ (posedge clock)
q <= d;
|
2 .Use blocking assignments (=) in combinational procedures:
3. Make sure that the event lists are complete
always @ (a or b) // this event list is missing signal sl
if (sl)
d = a;
else
d = b;
|
4. Take care of indentation. Develop your own identation guidelines and stick to them. Make sure others can read them. It helps readability and debugging greatly if it is done properly.
5. Comment code properly. The theory about good commenting is that you should be able to remove all functional code and the comments remaining should almost document the block you are designing.
// example of bad comments
// add a and b together
always @ (a or b)
c = a + b;
// Good commenting
// 8 bit unsigned adder for data signals ‘a’ and ‘b’
// output is sent to UART2
always @ (a or b)
c = a + b;
|
6. Always completely specify literals.
always @ (c)
if (c == 4’b0101)
a = 2’bxx;
else
a = 2’b10;
|
7. Use named port mapping when instantiating.
state_machine u1 (
.sm_in (in1),
.sm_clock (clk),
.reset (reset),
.sm_out (data_mux)
);
|
8. Don’t make the code any more complicated than it needs to be. Your priorities should be correctness, then readability and finally code efficiency.
'베릴로그' 카테고리의 다른 글
| Clock speed (0) | 2011/05/02 |
|---|---|
| Verilog VPI example (2) | 2011/03/21 |
| Verilog Coding Guidelines (2) | 2010/12/11 |
| 베릴로그 스니펫 Resettable D flip-flop (3) | 2010/11/14 |
| 베릴로그 스니펫 D flip-flop, Verilog D flip-flop (0) | 2010/11/13 |
| 베릴로그 스니펫 MUX, Verilog Snippet MUX (3) | 2010/05/06 |
댓글을 달아 주세요
5번은 좀 쩌네;; 3번이랑 6번은 같은 말 아니냐? 무슨 차이가 있는지 좀 알려줘 ㅠ
내가 알기로는 둘다 의도치 않은 latch가 생기는걸 막으려고 하는걸로 알고 있따능.